When an epitaxial semiconductor layer is grown upon a single crystal semiconductor substrate and there is a lattice parameter mismatch between the substrate material and the overlayer material and the overlayer thickness exceeds a critical thickness h.sub.c, then "misfit" dislocations are typically produced in the overlayer material.
It is well known that a perfect dislocation cannot simply terminate in the bulk of a crystal but rather must terminate at a free surface, upon itself by forming a loop, or at a node with another dislocation. Thus, misfit dislocations generally have a portion that lies in (or close to) the deposit/substrate interface, and frequently also a portion (typically the two ends of the dislocation) that is inclined with respect to the interface, substantially spans the thickness of the deposit layer and ends at the free surface of the deposit. The former portion is referred to as an "interfacial" dislocation and the latter as a "threading" dislocation.
Semiconductor structures of the described type ("strained layer heterostructures") are of considerable device interest since they potentially make possible previously unattainable devices and/or combinations of devices. For example, availability of high quality GaAs on Si would permit the combination of Si VLSI circuits with high speed GaAs circuits or with GaAs optical components. However, despite the recognized potential advantages of devices and/or circuits formed in strained layer semiconductor heterostructures, in most materials their practical utility has been limited by high dislocation densities. In particular, a relatively high density of threading dislocations is highly detrimental to device performance.
Prior art techniques for reducing interfacial and threading dislocation densities include "patterned" or mesa growth. In mesa epitaxy the lateral extent of deposit regions is limited such that the probability of the presence of dislocation sources in any given deposit region is low, and/or such that dislocations which do form can reach the boundary of the deposit region either during growth or during a subsequent heat treatment. See, for instance, U.S. patent application Ser. No. 561,744, filed Aug. 2, 1990 for E. A. Fitzgerald.
Another example of patterned epitaxy is British patent application GB 2,215,514A, incorporated herein by reference. It involves forming a pattern of dislocation-termination features ("mesas", but allegedly "trenches" are also possible) on the substrate surface.
As is well known, at least in substantially all strained layer heteroepitaxial systems of current technological interest, the vast majority of misfit dislocations are not free to move in arbitrary directions. Instead the dislocations are constrained to move in a predetermined direction [or in one of a small number (e.g., 2 or 3) of predetermined directions]. For instance, in overlayer materials that have the diamond cubic or the zincblende structure, the dislocations can glide only along the [011] or [011] interfacial direction if the substrate surface has (100) orientation.
The mesa growth technique can produce only relatively small, unconnected regions of epitaxial material on the substrate. The patterned epitaxy technique of GB 2,215,514A can overcome this particular shortcoming of the patterned growth technique, but has itself a significant shortcoming. In particular, the disclosed mesa geometry typically results in highly non-planar surfaces which can make subsequent metalization and/or other processing steps difficult. In general the technique of the '514A reference will result in material that may be ill-suited for IC processing or for the fabrication of optical and/or opto-electronic devices, especially large area devices such as photodetectors.
In view of the potential advantages of devices and combinations of devices that comprise strained layer semiconductor heterostructures, it would be highly desirable to have available such heterostructures that have low threading dislocation density and that are not subject to the above referred-to shortcomings of prior art patterned epitaxy heterostructures. This application discloses such heterostructures, together with techniques for making the heterostructures.